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A63L8336E-3.5F Datasheet(PDF) 7 Page - AMIC Technology

Part # A63L8336E-3.5F
Description  256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A63L8336E-3.5F Datasheet(HTML) 7 Page - AMIC Technology

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A63L8336
PRELIMINARY
(July, 2005, Version 0.0)
6
AMIC Technology, Corp.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx ( BW1 , BW2 , BW3 , or BW4 ) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X


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