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SY89538L Datasheet(HTML) 1 Page - Micrel Semiconductor

Part No. SY89538L
Description  3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY89538L Datasheet(HTML) 1 Page - Micrel Semiconductor

 
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SY89538L
3.3V Precision LVPECL and LVDS
Programmable Multiple Output Bank Clock
Synthesizer and Fanout Buffer with Zero Delay
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2005
M9999-101105-B
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89538L integrated programmable clock
synthesizer and fanout is part of a precision PLL-
based
clock
generation
family
optimized
for
enterprise switch, router, and multiprocessor server
applications. This family is ideal for generating
internal system timing requirements up to 750MHz for
multiple ASICs, FPGAs, and NPUs. These devices
integrate the following blocks into a single monolithic
IC:
PLL (Phase-Lock-Loop) based synthesizer
Zero-delay MUX and feedback capability
1:4 LVPECL fanout
1:3 LVDS fanout
Clock generator (dividers)
Logic translation (LVPECL, LVDS)
Five-independently programmable output
banks
This level of integration minimizes additive jitter and
part-to-part
skew
associated
with
discrete
alternatives, resulting in superior system-level timing
with
reduced
board
space
and
power.
For
applications that do not require a zero-delay function,
see the SY89537L.
All support documentation can be found on
Micrel’s web site at: www.micrel.com.
Applications
• Enterprise routers, switches, servers and
workstations
• Parallel processor-based systems
• Internal system clock generation for ASICs, NPUs
and FPGAs
Markets
• LAN/WAN
• Enterprise servers
• Test and measurement
Precision Edge
®
Features
• Integrated programmable synthesizer with multiple
output dividers, fanout buffers, and clock drivers
• Zero-delay capability: 29.375MHz to 756MHz
• Reference clock input: 9.325MHz to 756MHz
• Input MUX accepts a reference and a crystal
(XTAL) source
– Ideal for reference backup clock source or
system test frequency source
– Patent-pending unique input MUX isolates XTAL
and reference inputs which minimizes crosstalk
• Guaranteed AC performance:
– Output frequency range: 29.375MHz to 756MHz
– <150psPP total jitter
– <6psRMS cycle-to-cycle jitter (XTAL Input)
– <8psPP deterministic jitter
– <0.7psRMS crosstalk induced jitter
– <75ps output-to-output skew
• TTL/CMOS-compatible control logic
• Five-independently programmable output
frequency banks:
– Four differential LVPECL output banks
– One differential LVDS output bank with three
output pairs
• Output bank synchronization control pin
• Output enable
• 3.3V ±10% power supply (2.5V output capable)
• Guaranteed over the industrial temperature range
(-40°C to +85°C)
• Available in a 64-pin EPAD-TQFP


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