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ISL5927 Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL5927 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 13 page 4 Pin Descriptions PIN NO. PIN NAME PIN DESCRIPTION 11, 19, 26 AGND Analog ground. 13, 24 AVDD Analog supply (+2.7V to +3.6V). 28 CLK Clock Input. 27 DGND Connect to digital ground. 10 DVDD Digital supply (+2.7V to +3.6V). 20 FSADJ Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output current = 32 x VFSADJ/RSET. 14, 23 NC Not internally connected. Recommend no connect. 12, 25 ICOMP, QCOMP Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with a 0.1 µF capacitor. 1-8, 29-48 ID13-ID0, QD13-QD0 Digital data input ports. Bit 13 is most significant bit (MSB) and bit 0 is the least significant bit (LSB). 15, 22 IOUTA, QOUTA Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1. 16, 21 IOUTB, QOUTB Complementary current outputs of the device. Full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. 17 REFIO Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an external load. Use 0.1 µF cap to ground when internal reference is enabled. 18 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 9 SLEEP Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode. ISL5927 |
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