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PM29F002T-90JC Datasheet(PDF) 6 Page - PMC-Sierra, Inc |
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PM29F002T-90JC Datasheet(HTML) 6 Page - PMC-Sierra, Inc |
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6 / 21 page  Programmable Microelectronics Corp. Issue Date: March, 2001 Rev: 1.0 PMC Pm29F002 DEVICE OPERATION (CONTINUED) BLOCK ERASE The memory array is organized into five blocks: one 16 Kbytes boot block, two 8 Kbytes parameter blocks, one 96 Kbytes and one 128 Kbytes main blocks. A block erase operation allows to erase any individual block. Pre-programs the block is not required prior to block erase operation. If the boot block lockout feature is enable, the block erase command attempts to erase the boot block will be ignored. The block erase com- mand is similar to chip erase command except for the last bus cycle command where the block addresses are used to select the block for erasure and the input data to the I/Os is 30h. Each block erase operation erases one block. Block erase and chip erase are both internally controlled and timed. BYTE PROGRAMMING The programming is a four-bus-cycle operation and the data is programmed into the device (to a logical “0”) on a byte-by-byte basis. Please see Software Com- mand Definition in Table 4. A program operation is ac- tivated by writing the three-byte command sequence followed by one byte of data into the device. The ad- dress are latched on the falling edge of WE# or CE# whichever occurs later, and the data is latched on the rising edge of WE# or CE#, whichever occurs first. The internal control logic automatically handles the internal programming voltages and timing. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data# Polling of I/O7 or Toggle Bit of I/O6 can be used to de- tect when the programming operation is completed. CHIP ERASE The entire memory array can be erased through a chip erase operation. Pre-programs the device is not required prior to chip erase operation. Chip erase starts after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The device will return back to read mode after the completion of chip erase. When the boot block lockout feature is enabled, the boot block will not be erased during a chip erase operation. Only the parameter blocks and the main blocks will be erased. I/O7 DATA# POLLING The Pm29F002 provides Data# Polling feature to indicate the process or the completion of a program or erase cycle. During a program cycle, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is completed, the true data of the last loaded data is valid on all out- puts. During a block or chip erase operation, an attempt to read the device will result a “0” on I/O7. After the erase cycle is completed, an attempt to read the device will result a “1” on I/O7. I/O6 TOGGLE BIT The Pm29F002 also provides Toggle Bit feature as a method to detect the process or the end of a pro- gram or erase cycle. During a program or erase opera- tion, an attempt to read data from the device will result in I/O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase cycle. HARDWARE DATA PROTECTION Hardware data protection protects the device from unintentional erase or program operation. It is performed in the following ways: (a) VCC sense: if VCC is below 3.8 V (typical), the program function is inhibited. (b) Write inhibit: holding any of the signal OE# low, CE# high or WE# high inhibits a write cycle. (c) Noise filter: pulses of less than 20 ns (typical) on the WE# or CE# inputs will not initiate a write cycle. 6 |
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