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KM732V688L Datasheet(PDF) 2 Page - Samsung semiconductor

Part # KM732V688L
Description  64Kx32 Synchronous SRAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM732V688L Datasheet(HTML) 2 Page - Samsung semiconductor

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PRELIMINARY
Rev 2.0
KM732V688/L
64Kx32 Synchronous SRAM
- 2 -
Jun. 1998
WEc
WEd
64Kx32-Bit Synchronous Pipelined Burst SRAM
The KM732V688/L is a 2,097,152 bit Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of Pentium and Power PC based System.
It is organized as 64K words of 32 bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM732V688/L is fabricated using SAMSUNG
′s high per-
formance CMOS technology and is available in a 100pin QFP/
TQFP package. Multiple power and ground pins are utilized to
minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD=3.3V-5%/+10% Power Supply
• I/O Supply Voltage : 3.3V-5%/+10%
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
• L-Level Three-State Output.
• 100-QFP-1420C
• 100-TQFP-1420A
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
GW
BW
WEa
WEb
OE
ZZ
DQa0 ~ DQd7
BURST CONTROL
LOGIC
BURST
64Kx32
ADDRESS
CONTROL
OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
A
0~A′1
A0 ~ A1
A2~A15
A0~A15
REGISTER
FAST ACCESS TIMES
Parameter
Symbol
-13
-15
Unit
Cycle Time
tCYC
13
15
ns
Clock Access Time
tCD
7
7
ns
Output Enable Access Time
tOE
5
5
ns


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