PRELIMINARY

KM732V696/L

64Kx32 Synchronous SRAM

Rev 1.0

- 4 -

May 1997

FUNCTION DESCRIPTION

The KM732V696/L is a synchronous SRAM designed to support the burst address accessing sequence of the CISC and RISC

microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the

burst access is controlled by ADSC, ADSP and ADV and chip select pins.

The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with

ADV.

When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ

returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.

Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip

address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In

read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of

CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to

the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The

address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled Low. And ADSP is

All byte write is done by GW(regardless of BW and WEx.), and each byte write is performed by the combination of BW and WEx

when GW is High.

Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-

ples ADSP Low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled

Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the

next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte

write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa controls DQa0 ~ DQa7, WEb controls DQb0 ~ DQb7, WEc

controls DQc0 ~ DQc7, and WEd control DQd0 ~ DQd7. Read or write cycle may also be initiated with ADSC, instead of ADSP. The

differences between cycles initiated with ADSC and ADSP as are follows;

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external

address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state

of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is

selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

LBO PIN

HIGH

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

0

1

1

1

0

1

0

1

1

0

0

0

1

0

1

1

1

0

0

1

0

1

0

BURST SEQUENCE TABLE

(Linear Burst)

NOTE : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

LBO PIN

LOW

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

1

1

0

1

0

1

0

1

1

0

0

0

1

0

1

1

0

0

1

1

0

1

0