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SN74AUP1T58 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP1T58 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page www.ti.com AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time − ns † AUP1G08 data at C L = 15 pF Switching Characteristics at 25 MHz† Output Input SN74AUP1T98 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS SCES614A – OCTOBER 2004 – REVISED SEPTEMBER 2005 ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoStar™ – WCSP (DSBGA) Tape and reel SN74AUP1T98YEPR 0.23-mm Large Bump – YEP _ _ _TK_ NanoFree™ – WCSP (DSBGA) Tape and reel SN74AUP1T98YZPR –40 °C to 85°C 0.23-mm Large Bump – YZP (Pb-free) SOT (SOT-23) – DBV Tape and reel SN74AUP1T98DBVR HT6_ SOT (SC-70) – DCK Tape and reel SN74AUP1T98DCKR TK_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-to-1 data selector 5 2-input AND gate 6 2-input OR gate with one inverted input 7 2-input NAND gate with one inverted input 7 2-input AND gate with one inverted input 8 2-input NOR gate with one inverted input 8 2-input OR gate 9 Inverter 10 Noninverted buffer 11 Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity 2 |
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