MAY 2004

DSC-6109/0C

©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

1

18Mb Pipelined

QDR™II SRAM

Burst of 2

Advance

Information

IDT71P72204

IDT71P72104

IDT71P72804

IDT71P72604

Features

x

18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

x

Separate, Independent Read and Write Data Ports

-

Supports concurrent transactions

x

Dual Echo Clock Output

x

2-Word Burst on all SRAM accesses

x

DDR (Double Data Rate) Multiplexed Address Bus

-

One Read and One Write request per clock cycle

x

DDR (Double Data Rate) Data Buses

-

Two word burst data per clock on each port

-

Four word transfers per clock cycle (2 word

bursts on 2 ports)

x

Depth expansion through Control Logic

x

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

x

Scalable output drivers

-

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

-

Output Impedance adjustable from 35 ohms to 70

ohms

x

x

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

x

JTAG Interface

Description

memories with independent, double-data-rate (DDR), read and write

data ports. This scheme allows simultaneous read and write access for

the maximum device throughput, with two data items passed with each

read or write. Four data word transfers occur per clock cycle, providing

quad-data-rate (QDR) performance. Comparing this with standard SRAM

common I/O (CIO), single data rate (SDR) devices, a four to one in-

crease in data access is achieved at equivalent clock speeds. Consider-

ing that QDRII allows clock speeds in excess of standard SRAM de-

vices, the throughput can be increased well beyond four to one in most

applications.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

The QDRII has a single DDR address bus with multiplexed read and

write addresses. All read addresses are received on the first half of the

clock cycle and all write addresses are received on the second half of the

clock cycle. The read and write enables are received on the first half of

the clock cycle. The byte and nibble write signals are received on both

halves of the clock cycle simultaneously with the data they are controlling

on the data input bus.

The QDRII has echo clocks, which provide the user with a clock

Functional Block Diagram

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the

BW is a “nibble write” and there are 2

signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

ADD

REG

CTRL

LOGIC

CLK

GEN

(Note2)

SA

R

W

(Note3)

K

K

C

C

SELECT OUTPUT CONTROL

WRITE DRIVER

(Note4)

(Note2)

CQ

Q

(Note1)

(Note4)

18M

MEMORY

ARRAY

CQ

DATA

REG

(Note1)

(Note1)

6109 drw 16

DATA

REG

(Note1)

D