6.42

3

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 2

Commercial Temperature Range

Symbol

Pin Function

Description

D[X:0]

Input

Synchronous

Data input signals, sampled on the rising edge of K and

K clocks during valid write operations

2M x 8 -- D[7:0]

2M x 9 -- D[8:0]

1M x 18 -- D[17:0]

512K x 36 -- D[35:0]

Input

Synchronous

Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising

edge of

K clocks during write operations. Used to select which byte is written into the device during the

current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on

the same edge as the data. Deselecting a Byte Write Select will cause the corresponding b yte of data to be

ignored and not written in to the device.

2M x 9 --

1M x 18 --

512K x 36 --

NW0, NW1

Input

Synchronous

Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.

Sampled on the rising edge of the K and

K clocks during write operations. Used to select which nibble is

written into the device during the current portion of the write operations. Nibbles not written remain unaltered.

All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause

the corresponding nibble of data to be ignored and not written in to the device.

SA

Input

Synchronous

Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations.

Write addresses are sampled on the rising edge of

K clock during active write operations. These address

inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These

inputs are ignored when the appropriate port is deselected.

Q[X:0]

Output

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out

on the rising edge of both the C and

C clocks during Read operations or K and K when operating in single

clock mode. When the Read port is deselected, Q[X:0] are automatically three-stated.

W

Input

Synchronous

Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted

active, a write operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause

D[X:0] to be ignored.

R

Input

Synchronous

Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a

Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the

pending access is allowed to complete and the output drivers are automatically three-stated following the next

rising edge of the C clock. Each read access consists of a burst of two sequential transfer.

C

Input Clock

Positive Output Clock Input. C is used in conjunction with

C to clock out the Read data from the device. C

and

C can be used together to deskew the flight times of various devices on the board back to the controller.

See application example for further details.

C

Input Clock

Negative Output Clock Input.

C is used in conjunction with C to clock out the Read data from the device. C

and

C can be used together to deskew the flight times of various devices on the board back to the controller.

See application example for further details.

K

Input Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to

drive out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.

K

Input Clock

Negative Input Clock Input.

K is used to capture synchronous inputs being presented to the device and to

drive out data thro ugh Q[X:0] when in single clock mode.

CQ,

CQ

Output Clock

Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals are free running and do not stop when

the output data is tri-stated.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and

This pin cannot be connected directly to GND or left unconnected.

6109 tbl 02a

Pin Definitions