PRELIMINARY

K6T1008C2C Family

CMOS SRAM

Revision 2.0

November 1997

2

128K x8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6T1008C2C families are fabricated by SAMSUNG

′s

advanced CMOS process technology. The families support

various operating temperature ranges and have various

package types for user flexibility of system design. The fami-

lies also support low data retention voltage for battery back-

up operation with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 128K x8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-DIP-600, 32-SOP-525,

32-TSOP1-0820F/R

PIN DESCRIPTION

PRODUCT FAMILY

Product Family

Operating Temperature

Vcc Range

Speed

Power Dissipation

PKG Type

Standby

Operating

K6T1008C2C-L

Commercial(0~70

°C)

4.5~5.5V

55/70ns

50

µA

10

µA

60mA

32-DIP, 32-SOP

32-TSOP1-F/R

K6T1008C2C-B

K6T1008C2C-P

Industrial(-40~85

°C)

70ns

50

µA

15

µA

32-SOP

32-TSOP1-F/R

K6T1008C2C-F

FUNCTIONAL BLOCK DIAGRAM

32-TSOP

Type1 - Reverse

A11

A9

A8

A13

WE

CS2

A15

VCC

N.C

A16

A14

A12

A7

A6

A5

A4

OE

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A0

A1

A2

A3

32-TSOP

Type1 - Forward

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

N.C

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

VSS

VCC

A15

CS2

WE

A13

A8

A9

A11

OE

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

32-DIP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32-SOP

A11

A9

A8

A13

WE

CS2

A15

VCC

N.C

A16

A14

A12

A7

A6

A5

A4

OE

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A0

A1

A2

A3

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

1024 rows

128

×8 columns

I/O Circuit

Column select

Clk gen.

Row

select

A0

A1

A2

A3

A9

A11

A10

A4

A5

A6

A7

A8

A12

A14

Data

cont

A13

A15

A16

CS1

WE

OE

Control

logic

CS2

Data

cont

Name

Function

Name

Function

Chip Select Inputs

Data Inputs/Outputs

OE

Output Enable

Vcc

Power

WE

Write Enable Input

Vss

Ground

Address Inputs

N.C

No Connection