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ISL6251AHRZ Datasheet(PDF) 17 Page - Intersil Corporation |
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ISL6251AHRZ Datasheet(HTML) 17 Page - Intersil Corporation |
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17 / 20 page  17 FN9202.1 June 17, 2005 The voltage gain with open current loop is: Where , VFB is the feedback voltage of the voltage error amplifier. The Voltage loop gain with current loop closed is given by: If Ti(S)>>1, then it can be simplified as follows: , From the above equation, it is shown that the system is a single order system, which has a single pole located at before the half switching frequency. Therefore, simple type II compensator can be easily used to stabilize the system. Figure 15 shows the voltage loop compensator, and its transfer function is expressed as follows: FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR FIGURE 15. VOLTAGE LOOP COMPENSATOR where Compensator design goal: • High DC gain • Loop bandwidth fc: • Gain margin: >10dB • Phase margin: 40° The compensator design procedure is as follows: 1. Put compensator zero at: 2. Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower. The loop gain Tv(S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R1 is determined by: where gm is the trans-conductance of the voltage loop error amplifier. Compensator capacitor C1 is then given by: Example: Vin=19V, Vo=16.8V, Io=2.6A, fs=300kHz, Co=10µF/10mΩ, L=10µH, gm=250µs, RT=0.2Ω, VFB=2.1V, VPWM=VIN/11, fc=20kHz, then compensator resistance R1=8.0kΩ. Choose R1=10kΩ. Put the compensator zero at 1.5kHz. The compensator capacitor is C1=10nF. Therefore, choose voltage loop compensator: R1=10K, C1=10nF. PCB Layout Considerations Power and Signal Layers Placement on the PCB As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. As an example, layer arrangement on a 4-layer board is shown below: 1. Top Layer: signal lines, or half board for signal lines and the other half board for power lines 2. Signal Ground 3. Power Layers: Power Ground 4. Bottom Layer: Power MOSFET, Inductors and other Power traces Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will () () S A S F KF ) S ( T v 1 m v = o FB V V K = () () S T 1 S T ) S ( L i v v + = () () S H S A S 1 S 1 R R R V V ) S ( L e v p esr T L o o FB v ω ω + + + = o o p C R 1 ≈ ω p ω dˆ Vin dˆ IL in vˆ in iˆ L + 1:D L iˆ Co Rc Ro -Av(S) dˆ comp vˆ RT Fm He(S) + Ti(S) K o vˆ Tv(S) dˆ Vin dˆ IL in vˆ in iˆ L + 1:D L iˆ Co Rc Ro -Av(S) dˆ comp vˆ RT Fm He(S) + Ti(S) K o vˆ Tv(S) - + R1 C1 V REF VFB Vo gm VCOMP - + Vo - + R1 C1 V REF VFB Vo gm VCOMP - + Vo () SC S 1 g vˆ vˆ S A 1 cz m FB comp v ω + = = , C R 1 1 1 cz = ω s f 20 1 5 1 − () o o cz C R 1 3 1 − = ω FB m T o o c 1 V g R C V f 2 R π = cz 1 1 R 1 C ω = ISL6251, ISL6251A |
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