6

FN9189.1

July 22, 2005

Functional Pin Description

5VSBY (Pin 1)

5VSBY is the bias supply of the ISL6548A. It is typically

connected to the 5V standby rail of an ATX power supply.

During S4/S5 sleep states the ISL6548A enters a reduced

5VSBY supply. The supply to 5VSBY should be locally

bypassed using a 0.1

µF capacitor.

P12V (Pin 3)

powered by P12V. P12V is not required during S3/S4/S5

operation. P12V is typically connected to the +12V rail of an

ATX power supply.

GND (Pins 4, 27, 29)

The GND terminals of the ISL6548A provide the return path

ground currents are conducted directly through the exposed

paddle of the QFN package which must be electrically

connected to the ground plane through a path as low in

inductance as possible.

PWM CONTROLLER GATE DRIVERS

UGATE and LGATE Source

--0.8

-

A

UGATE and LGATE Sink

-0.8

-

A

VTT REGULATOR

Upper Divider Impedance

-2.5

-

k

Ω

Lower Divider Impedance

-2.5

-

k

Ω

Periodic load applied with 30% duty cycle and

10ms period using ISL6548A_6506EVAL1

evaluation board (see Application Note AN1124)

-3

-

3

A

LINEAR REGULATORS

DC Gain

Guaranteed By Design

-

80

-

dB

Gain Bandwidth Product

GBWP

15

-

-

MHz

Slew Rate

SR

-

6

-

V/

µs

DRIVEn High Output Voltage

DRIVEn Unloaded

9.75

10.0

-

V

DRIVEn Low Output Voltage

-

0.16

0.50

V

DRIVEn High Output Source Current

-

1.7

2.6

mA

DRIVEn Low Output Sink Current

-

1.20

2.00

mA

VIDPGD

S0

.725

.740

-

V

S0

-

0.700 0.715

V

PROTECTION

OCSET Current Source

18

20

22

µA

By Design

-3.3

-

3.3

A

S0/S3

-

115

-

%

S0/S3

-

85

-

%

-

115

-

%

-

85

-

%

S0

-

85

-

%

S0

-

85

-

%

Thermal Shutdown Limit

By Design

-

140

-

°C

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams and Typical Application Schematics (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ISL6548A