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ISL6614CBZA-T Datasheet(PDF) 10 Page - Intersil Corporation

Part # ISL6614CBZA-T
Description  Dual Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6614CBZA-T Datasheet(HTML) 10 Page - Intersil Corporation

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10
FN9155.4
July 25, 2005
SO14 package is approximately 1W at room temperature,
while the power dissipation capacity in the QFN packages,
with an exposed heat escape pad, is around 2W. See Layout
Considerations paragraph for thermal transfer improvement
suggestions. When designing the driver into an application, it
is recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses due to
the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with EQs. 2 and 3, respectively,
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; NQ1
and NQ2 are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltages for both upper and
lower FETs, respectively. The IQ*VCC product is the
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (RG1 and RG2) and the internal gate resistors
(RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
PQg_TOT
2PQg_Q1
2PQg_Q2
IQ VCC
++
=
(EQ. 2)
PQg_Q1
QG1 PVCC2
VGS1
--------------------------------------- FSW
NQ1
=
PQg_Q2
QG2 PVCC2
VGS2
--------------------------------------- FSW
NQ2
=
IDR
QG1 NQ1
VGS1
------------------------------
QG2 NQ2
VGS2
------------------------------
+



FSW 2
IQ
+
=
(EQ. 3)
PDR
2P
DR_UP
2P
DR_LOW
IQ VCC
++
=
(EQ. 4)
PDR_UP
RHI1
RHI1 REXT1
+
--------------------------------------
RLO1
RLO1 REXT1
+
----------------------------------------
+


 PQg_Q1
2
---------------------
=
PDR_LOW
RHI2
RHI2 REXT2
+
--------------------------------------
RLO2
RLO2 REXT2
+
----------------------------------------
+


 PQg_Q2
2
---------------------
=
REXT1
RG1
RGI1
NQ1
-------------
+
=
REXT2
RG2
RGI2
NQ2
-------------
+
=
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
RGI1
RG1
BOOT
RHI1
CDS
CGS
CGD
RLO1
PHASE
PVCC
PVCC
Q2
D
S
G
RGI2
RG2
RHI2
CDS
CGS
CGD
RLO2
ISL6614


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