2

FN8241.2

August 15, 2005

Block Diagram

7-BIT

WIPER

REGISTER

7-BIT

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

ONE

OF

128

DECODER

RESISTOR

ARRAY

SDA

SCL

TRANSFER

GATES

CONTROL

AND

MEMORY

V-

SIMPLE BLOCK DIAGRAM

DETAILED BLOCK DIAGRAM

0

1

2

124

125

126

127

(VOLATILE)

SLAVE

ADDRESS

DECODE

A1

A0

SDA

SCL

A1

A0

GND

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1

SDA

active low outputs.

2

V-

Negative supply voltage for the potentiometer wiper control.

3

GND

Ground.

4

A1

5

A0

6RH

A fixed terminal for one end of the potentiometer resistor.

7RW

The wiper terminal which is equivalent to the movable terminal of a potentiometer.

8RL

A fixed terminal for one end of the potentiometer resistor.

Positive logic supply voltage

10

SCL

ISL95711