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X1226V8T1 Datasheet(PDF) 11 Page - Intersil Corporation |
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X1226V8T1 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 25 page 11 FN8098.2 September 15, 2005 Figure 4. Valid Start and Stop Conditions Figure 5. Acknowledge Response From Receiver DEVICE ADDRESSING Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM array. Slave bits ‘1101’ access the CCR. When shipped from the factory, EEPROM array is UNDEFINED, and should be programmed by the cus- tomer to a known state. Bit 3 through Bit 1 of the slave byte specify the device select bits. These are set to ‘111’. The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 6. After loading the entire Slave Address Byte from the SDA bus, the X1226 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power- up the internal address counter is set to address 0h, so a current address read of the EEPROM array starts at address 0. When required, as part of a random read, the master must supply the 2 Word Address Bytes as shown in Figure 6. In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. That is if the random read is from the array the slave byte must be 1010111x in both instances. Similarly, for a random read of the Clock/Control Registers, the slave byte must be 1101111x in both places. SCL SDA Start Stop SCL from Master Data Output from Transmitter Data Output from Receiver 8 1 9 Start Acknowledge X1226 |
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