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X3100 Datasheet(PDF) 8 Page - Intersil Corporation |
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X3100 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 40 page 8 FN8110.0 April 11, 2005 Figure 2. Power-up Timing (Initial Power-up or after Sleep Mode) VCC VRGO TOC 2ms (Typ.) TPUR 5V±10% (Stable and Repeatable) 0V 0V VRGO Tuned to 5V±0.5% VRGS Voltage Regulator Output Status OCDS Over-current Detection Status VRGS+OCDS 1 = X3100/1 in Over-Current Protection Mode 0 = X3100/1 NOT in Over-Current Protection Mode 0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned 1 = X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned Status Register Bit 0 1 0 5V VSLR 1 0 1 AS2_AS0 0 (Internal Signal) (Internal Signal) CCES+OVDS Status Register Bit 2 (SWCEN = 0) OVDS Status Register Bit 2 (SWCEN = 1) 0 0 TOV+200ms 1 1 SPI PORT TOV + 200ms OR TUV + 200ms (whichever is longer) 0 = VCELL > VCE OR X3100/1 NOT in Over-charge Protection Mode 1 = VCELL < VCE OR X3100/1 in Over-charge Protection Mode 0 = X3100/1 NOT in Over-charge Protection Mode 1 = X3100/1 in Over-charge Protection Mode Charge, Discharge FETs can be turned on here. Any Read or Write Operation, except turn-on of FETs can start here. X3100, X3101 |
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