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X4003S8 Datasheet(PDF) 6 Page - Intersil Corporation |
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X4003S8 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 17 page 6 FN8113.0 March 15, 2005 RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the control register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the control register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes the control register will be ignored (no acknowledge will be issued after the data byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watchdog timer. The options are shown below. Writing to the Control Register Changing any of the nonvolatile bits of the control regis- ter requires the following steps: – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation pre- ceeded by a start and ended with a stop.) – Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop.) – Write a value to the control register that has all the control bits set to the desired state. This can be rep- resented as 0xy0 0010 in binary, where xy are the WD bits. (Operation preceeded by a start and ended with a stop.) Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then the RWEL bit is set, but the WD1 and WD0 bits remain unchanged. Writing a second byte to the control reg- ister is not allowed. Doing so aborts the write opera- tion and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this fam- ily operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 5. WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 Disabled (factory setting) X4003, X4005 |
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