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X4045M8 Datasheet(PDF) 8 Page - Intersil Corporation

Part # X4045M8
Description  CPU Supervisor with 4kbit EEPROM
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X4045M8 Datasheet(HTML) 8 Page - Intersil Corporation

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8
FN8118.1
September 30, 2005
Figure 5. VTRIP Programming Sequence
Control Register
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte
write operation directly to the address of the register
and only one data byte is allowed for each register
write operation. Prior to writing to the control register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register".
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4043/45 will
not acknowledge any data bytes written after the first
byte is entered.
VTRIP Programming
Power-down
Actual VTRIP
Desired VTRIP
DONE
Set Higher VTRIP Sequence
Error < MDE
| Error | < | MDE |
YES
NO
Error > MDE+
the Device
Desired
Present Value ?
VTRIP <
Execute
No
YES
Execute
VTRIP Reset Sequence
Set VCC = desired VTRIP
New VCC applied =
Old VCC applied + | Error |
New VCC applied =
Old VCC applied – | Error |
Execute Reset VTRIP
Sequence
Output Switches?
Let: MDE = Maximum Desired Error
MDE+
Desired Value
MDE
Acceptable
Error Range
Error = Actual – Desired
(RESET)
Ramp VCC
= Error
X4043, X4045


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