2

FN8122.0

March 29, 2005

PIN CONFIGURATION

PIN FUNCTION

SDA

SCL

3

2

4

1

6

7

5

8

8-Pin JEDEC SOIC

WP

RST/RST

SCL

RST/RST

3

2

4

1

6

7

5

8

WP

SDA

8-Pin TSSOP

Pin

(SOIC)

Pin

(TSSOP)

Name

Function

13

Device Select Input

24

Device Select Input

35

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW

longer than the selectable Watchdog time out period. A falling edge on SDA, while

SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up-

power-up and remains active for 250ms after the power supply stabilizes.

46

Ground

57

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the de-

vice. It has an open drain output and may be wire ORed with other open drain or

open collector outputs. This pin requires a pull up resistor and the input buffer is al-

ways active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

68

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

71

WP

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the

control register.

82

Supply Voltage

X4323, X4325