 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
X4643V8I Datasheet(PDF) 3 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
X4643V8I Datasheet(HTML) 3 Page - Intersil Corporation |
|
|
3 / 21 page  3 FN8123.0 March 29, 2005 PRINCIPLES OF OPERATION Power-On Reset Application of power to the X4643/5 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/RESET allowing the system to begin operation. LOW VOLTAGE MONITORING During operation, the X4643/5 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time out period to prevent a RESET/RESET signal. The state of two nonvolatile control bits in the Status Register deter- mine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. EEPROM INADVERTENT WRITE PROTECTION When RESET/RESET goes active as a result of a low voltage condition or Watchdog Timer Time Out, any in- progress communications are terminated. While RESET/RESET is active, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VCC THRESHOLD RESET PROCEDURE The X4643/5 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applica- tions where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4643/5 threshold may be adjusted. The procedure is described below, and uses the application of a nonvol- atile control signal. Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set) 01 2 3 45 67 SCL SDA A0h 01 2 3 45 67 00h WP VP = 12-15V 01 2 3 45 67 01h 01 2 3 4 5 6 7 00h X4643, X4645 |
Similar Part No. - X4643V8I |
|
Similar Description - X4643V8I |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
