X9119TV14 datasheet(6/18 Pages) INTERSIL

Part #	X9119TV14

Description	Single Supply/Low Power/1024-Tap/2-Wire Bus

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Manufacturer	INTERSIL [Intersil Corporation]

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6

FN8162.2

September 15, 2005

Instruction and Register Description

DEVICE ADDRESSING: IDENTIFICATION BYTE

(ID AND A)

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier. The ID[3:0] bits is the device id for the

X9119; this is fixed as 0101[B] (refer to Table 1).

The A2–A0 bits in the ID byte is the internal slave

address. The physical device address is defined by

the state of the A2–A0 input pins. The slave address is

externally specified by the user. The X9119 compares

the serial data stream with the address input state; a

successful compare of both address bits is required for

the X9119 to successfully continue the command

sequence. Only the device which slave address

matches the incoming device address sent by the

master executes the instruction. The A2–A0 inputs

can be actively driven by CMOS input signals or tied to

VCC or VSS. The R/W bit is the LSB and is be used to

program the device for read or write operations.

INSTRUCTION BYTE AND REGISTER SELECTION

The next byte sent to the X9119 contains the

instruction and register pointer information. The three

most significant bits are used provide the instruction

opcode (IOP[2:0]). The RB and RA bits point to one of

the four registers. The format is shown below in

Table 2.

Table 3 provides a complete summary of the

instruction set opcodes.

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

ID3

ID2

ID1

ID0

A2

A1

A0

R/W

01

(MSB)

(LSB)

Device Type

Identifies

Internal Slave

Address

Read or

Write Bit

I2

I1

I0

0

RB

RA

0

(MSB)

(LSB)

Instruction

Opcode

Register

Selection

Register Selected

RB

RA

DR0

0

DR1

0

1

DR2

1

0

DR3

1

X9119

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