1

®

FN8169.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

X9259

Single Supply/Low Power/256-Tap/2-Wire bus

Quad Digitally-Controlled (XDCP™)

Potentiometers

The X9259 integrates four digitally controlled potentio-

meters (XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are imple-mented

with a combination of resistor elements and CMOS switches.

The position of the wipers are controlled by the user through

the 2-wire bus interface. Each potentiometer has associated

with it a volatile Wiper Counter Register (WCR) and four

non-volatile Data Registers that can be directly written to and

read by the user. The content of the WCR controls the

position of the wiper. At power-up, the device recalls the

content of the default Data Registers of each DCP (DR00,

DR10, DR20, and DR30) to the corresponding WCR.

The XDCP can be used as a three-terminal potentiometer or

as a two terminal variable resistor in a wide variety of

applications including control, parameter adjustments, and

signal processing.

Features

• Four Separate Potentiometers in One Package

• 256 Resistor Taps–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and

Transfer Operations of the Potentiometer

• Wiper Resistance: 100

• 4 Non-volatile Data Registers for Each Potentiometer

• Non-volatile Storage of Multiple Wiper Positions

• Standby Current < 5µA Max

•50k

Ω, 100kΩ versions of Total Resistance

• Endurance: 100,000 Data Changes per Bit per Register

• 100 yr. Data Retention

• Single Supply Version of X9258

• 24 Ld SOIC, 24 Ld TSSOP

• Low Power CMOS

• Pb-Free Plus Anneal Available (RoHS Compliant)

Functional Diagram

POWER UP,

INTERFACE

CONTROL

AND

2-Wire

DCP0

A1

SDA

SCL

A3

A2

WP

WCR0

DR00

DR01

DR02

DR03

DCP1

WCR1

DR10

DR11

DR12

DR13

DCP2

WCR2

DR20

DR21

DR22

DR23

DCP3

WCR3

DR30

DR31

DR32

DR33

A0

Interface

STATUS

Data Sheet

September 16, 2005