7

FN8171.2

September 14, 2005

Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

DEVICE DESCRIPTION

Instructions

The first byte sent to the X9261 from the host,

following a CS going HIGH to LOW, is called the

Identification Byte. The most significant four bits of the

slave address are a device type identifier. The ID[3:0]

bits is the device id for the X9261; this is fixed as

0101[B] (refer to Table 3).

The AD[3:0] bits in the ID byte is the internal slave

address. The physical device address is defined by

the state of the A3 - A0 input pins. The slave address

is externally specified by the user. The X9261

compares the serial data stream with the address

input state; a successful compare of both address bits

is required for the X9261 to successfully continue the

command sequence. Only the device which slave

address matches the incoming device address sent

by the master executes the instruction. The A3-A0

inputs can be actively driven by CMOS input signals

The next byte sent to the X9261 contains the instruction

and register pointer information. The three most

significant bits are used provide the instruction opcode

(I[3:0]). The RB and RA bits point to one of the four

Data Registers of each associated XDCP. The least

significant bit points to one of two Wiper Counter

Registers or Pots.The format is shown below in Table 4.

Table 3. Identification Byte Format

Table 4. Instruction Byte Format

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

VVVVVVVV

(MSB)

(LSB)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

NV

NV

NV

NV

NV

NV

NV

NV

MSB

LSB

ID3

ID2

ID1

ID0

A3

A2

A1

A0

010

1

(MSB)

(LSB)

Device Type

Identifier

Slave Address

I3

I2

I1

I0

RB

RA

0

P0

(MSB)

(LSB)

Instruction

Register

Pot Selection

Opcode

Selection

(WCR Selection)

Data

X9261