X9268US24I-2.7 datasheet(6/24 Pages) INTERSIL

Part #	X9268US24I-2.7

Description	Dual Supply/Low Power/256-Tap/2-Wire Bus

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Manufacturer	INTERSIL [Intersil Corporation]

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6

FN8172.1

June 21, 2005

SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9268 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9268 will be considered a

slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods. SDA state changes during SCL

HIGH are reserved for indicating start and stop

conditions. See Figure 2.

Start Condition

All commands to the X9268 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH. The X9268 continuously monitors

the SDA and SCL lines for the start condition and will

not respond to any command until this condition is

met. See Figure 2.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

The X9268 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9268 will respond with a final acknowledge.

See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

1

89

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

X9268

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