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X9261US24-2.7 Datasheet(PDF) 4 Page - Intersil Corporation |
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X9261US24-2.7 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 21 page  4 FN8171.2 September 14, 2005 PIN CONFIGURATION PIN ASSIGNMENTS PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9261. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the 4-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9261. CHIP SELECT (CS) When CS is HIGH, the X9261 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9261, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Pin (SOIC/ TSSOP) Symbol Function 1 SO Serial Data Output for SPI bus 2 A0 Device Address for SPI bus. 3 NC No Connect. 4 NC No Connect. 5 NC No Connect. 6 NC No Connect. 7VCC System Supply Voltage 8RL0 Low Terminal for Potentiometer 0. 9RH0 High Terminal for Potentiometer 0. 10 RW0 Wiper Terminal for Potentiometer 0. 11 CS Device Address for SPI bus. 12 WP Hardware Write Protect 13 SI Serial Data Input for SPI bus 14 A1 Device Address for SPI bus. 15 RL1 Low Terminal for Potentiometer 1. 16 RH1 High Terminal for Potentiometer 1. 17 RW1 Wiper Terminal for Potentiometer 1. 18 VSS System Ground 19 NC No Connect 20 NC No Connect 21 NC No Connect 22 NC No Connect 23 SCK Serial Clock for SPI bus 24 HOLD Device select. Pause the SPI serial bus. SO A0 NC NC VCC RL0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 HOLD SCK NC NC NC NC VSS RW1 RH1 RL1 SOIC/TSSOP X9261 NC 14 13 11 12 NC RH0 RW0 CS A1 SI WP X9261 |
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