X9408YV24Z datasheet(4/21 Pages) INTERSIL

Part #	X9408YV24Z

Description	Low Noise/Low Power/2-Wire Bus

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Manufacturer	INTERSIL [Intersil Corporation]

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4

FN8191.2

September 19, 2005

PRINCIPLES OF OPERATION

The

X9408

is

a

highly

integrated

microcircuit

incorporating four resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Serial Interface

The X9408 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9408 will be considered a

slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods (tLOW). SDA state changes during

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9408 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH (tHIGH). The X9408 continuously

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

The X9408 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9408 will respond with a final acknowledge.

Array Description

The X9408 is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RLinputs).

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(RW) output. Within each individual array only one

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier (refer to Figure 1 below). For the X9408

this is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device

address. The physical device address is defined by

the state of the A0 - A3 inputs. The X9408 compares

the serial data stream with the address input state; a

successful compare of all four address bits is required

for the X9408 to respond with an acknowledge. The

A0 - A3 inputs can be actively driven by CMOS input

signals or tied to VCC or VSS.

1

00

A3

A2

A1

A0

Device Type

Identifier

Device Address

1

X9408

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