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X9400YV24I Datasheet(PDF) 3 Page - Intersil Corporation

Part # X9400YV24I
Description  Low Noise/Low Power/SPI Bus
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X9400YV24I Datasheet(HTML) 3 Page - Intersil Corporation

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3
FN8189.1
March 31, 2005
PIN NAMES
DEVICE DESCRIPTION
The
X9400
is
a
highly
integrated
microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9400 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of sixty-four
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
global XFR data register instructions (parallel load); it
can be modified one
step at a time by the
increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9400 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0 - A1
Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pins (terminal
equivalent)
VW0/RW0 - VW1/RW1
Potentiometer Pins (wiper
equivalent)
WP
Hardware Write Protection
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
X9400


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