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X9420WP Datasheet(PDF) 5 Page - Intersil Corporation |
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X9420WP Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 20 page  5 FN8195.0 March 7, 2005 The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits are defined as 0. Two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register — This instruction transfers the contents of one speci- fied Data Register to the Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This instruction transfers the contents of the Wiper Counter Register to the specified associated Data Register. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9420; either between the host and one of the Data Registers or directly between the host and the WCR. These instructions are: – Read Wiper Counter Register—read the current wiper position of the pot, – Write Wiper Counter Register—change current wiper position of the pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and Figure 8. Figure 4. Two-Byte Instruction Sequence 0101 110A0 I3 I2 I1 I0 R1 R0 0 0 SCK SI CS X9420 |
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