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X9401WV24Z-2.7 Datasheet(PDF) 6 Page - Intersil Corporation |
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X9401WV24Z-2.7 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 20 page  6 FN8190.2 September 23, 2005 Figure 2. Instruction Byte Format The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) selects which one of the four potenti- ometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register—This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register —This transfers the contents of all specified Data Registers to the associated Wiper Counter Regis- ters. – Global XFR Wiper Counter Register to Data Register—This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. The basic sequence of the two byte instructions is illus- trated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated reg- isters; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9401; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – Read Wiper Counter Register— read the current wiper position of the selected pot, – Write Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 4 and Figure 5. The final command is Increment/Decrement. It is dif- ferent from the other commands, because it’s length is indeterminate. Once the command is issued, the mas- ter can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tun- ing capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 6 and Figure 7. I1 I2 I3 I0 R1 R0 P1 P0 Pot Select Register Select Instructions X9401 |
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