3

FN8114.0

April 28, 2005

PRINCIPLES OF OPERATION

Power On Reset

Applying power to the X40030, X40031, X40034,

X40035 activates a Power On Reset Circuit that pulls

the RESET/RESET pins active. This signal provides

several benefits.

– It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

(X40031, X40035) and RESET (X40030, X40034) pin

allowing the system to begin operation.

Figure 1. Connecting a Manual Reset Push-Button

Manual Reset

By connecting a push-button directly from MR to

ground, the designer adds manual system reset capa-

bility. The MR pin is LOW while the push-button is

closed and RESET/RESET pin remains HIGH/LOW

after.

During operation, the X40030, X40031, X40034,

X40035

monitors

the

RESET/RESET if supply voltage falls below a preset

microprocessor from operating in a power fail or

brownout

condition.

The

RESET/RESET

signal

remains active until the voltage drops below 1V. It also

Low Voltage V2 Monitoring

The X40030 also monitors a second voltage level and

asserts V2FAIL if the voltage falls below a preset mini-

RESET to prevent the microprocessor from operating

in a power fail or brownout condition or used to inter-

rupt the microprocessor with notification of an impend-

ing power failure.

For the X40030 and X40031 the V2FAIL signal

remains active until the V2MON drops below 1V

(V2MON falling). It also remains active until V2MON

Ground

8SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an

open drain output and may be wire ORed with other open drain or open collector outputs. This pin

requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW

and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within

the watchdog time out period results in WDO going active.

9SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

10

WP

Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers).

It has an internal pull down resistor. (>10M

Ω typical)

11

V3MON

LOW. This input can monitor an unregulated power supply with an external resistor divider or can

not used. The V3MON comparator is supplied by the V3MON input.

12

V3FAIL

13

WDO

WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-

dog timer goes active.

14

Supply Voltage.

Pin

Name

Function

MR

System

Reset

Manual

Reset

X40030/34

RESET

X40030, X40031, X40034, X40035