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X80001 Datasheet(PDF) 5 Page - Intersil Corporation |
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X80001 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 37 page  5 FN8148.0 March 18, 2005 Equivalent A.C. Output Load Circuit tMRHD Delay from MRH disable to GATE reaching 1V IGATE = 60µA, No Load 1.8 2.6 µs tRESET_E Delay from PWRGD or ViGOOD to RESET valid LOW 1 µs tQC Delay from IGQ1 and IGQ0 to valid Gate pin current 1 µs tSC_RETRY Delay between retries TSC1 = 0; TSC0 = 0 90 100 110 ms tNF Noise Filter for Overcurrent TF1 = 0; TF0 = 1 4.5 5 5.5 µs tDPOR Device Delay before Gate assertion 45 50 55 ms tSPOR Delay after PWRGD and all ViGOOD signals are active before RESET assertion TPOR1 = 0; TPOR0 = 0 90 100 110 ms tTO ViGOOD turn off time 50 ns tPDHLPG (Note 1) Delay from Drain good to PWRGD LOW Gate = VDD 1 µs tPDLHPG (Note 1) Delay from Drain fail to PWRGD HIGH Gate = VDD 1 µs tPGHLPG (Note 1) Delay from Gate good to PWRGD LOW Drain = VEE 1 µs tPGLHPG (Note 1) Delay from Gate fail to PWRGD HIGH Drain = VEE 1 µs NOTE: 1. This parameter is based on characterization data. Electrical Specifications Standard Settings Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A.C. Test Conditions Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load 5V SDA 30pF 4.6k Ω RESET 30pF V1GOOD, 5V 4.6k Ω 30pF V2GOOD, V3GOOD, V4GOOD, FAR 5V 4.6k Ω PWRGD X80000, X80001 |
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Similar Description - X80001 |
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