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X40435V14-A Datasheet(PDF) 11 Page - Intersil Corporation |
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X40435V14-A Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 24 page 11 FN8251.0 July 29, 2005 Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the mas- ter begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowl- edge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 13. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Ran- dom Reads, and Sequential Reads. Figure 11. Page Write Operation Figure 12. Writing 12 bytes to a 16-byte page starting at location 10. S t a r t S t o p Slave Address Byte Address Data (n) A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 Data (1) A C K (1 ≤ n ≤ 16) 10 1 0 0 0 address address 10 5 Bytes n-1 7 Bytes address = 6 address pointer ends here Addr = 7 X40430, X40431, X40434, X40435 |
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