TPS330718M

TRIPLE PROCESSOR SUPERVISORS

SGLS133A − JANUARY 2003 − REVISED DECEMBER 2003

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 2 V to 6 V,

IOH = −20 µA

VDD– 0.2V

VOH

High-level output voltage

VDD = 3.3 V,

IOH = −2 mA

VDD– 0.4V

V

VOH

High-level output voltage

VDD = 6 V,

IOH = −3 mA

VDD– 0.4V

V

VDD = 2 V to 6 V,

IOL = 20 µA

0.2

VOL

Low-level output voltage

VDD = 3.3 V,

IOL = 2 mA

0.4

V

VOL

Low-level output voltage

VDD = 6 V,

IOL = 3 mA

0.4

Power-up reset voltage (see Note 2)

VDD ≥ 1.1 V,

IOL = 20 µA

0.4

V

Negative-going input threshold voltage

VSENSE3

1.22

1.25

1.29

V

VIT−

Negative-going input threshold voltage

(see Note 3)

VSENSE2

VDD = 2 V to 6 V

1.64

1.68

1.73

V

VIT−

(see Note 3)

VSENSE1

VDD = 2 V to 6 V

2.86

2.93

3.02

V

VIT− = 1.25 V

2

10

30

Vhys

Hysteresis at VSENSEn input

VIT− = 1.68 V

2

15

40

mV

Vhys

Hysteresis at VSENSEn input

VIT− = 2.93 V

3

30

60

mV

MR

MR = 0.7

× VDD,

VDD = 6 V

−130

−180

IH

High-level input current

SENSE1

VSENSE1 = VDD = 6 V

5

8

µA

IH

High-level input current

SENSE2

VSENSE2 = VDD = 6 V

6

9

µA

SENSE3

VSENSE3 = VDD

−25

25

nA

IL

Low-level input current

MR

MR = 0 V,

VDD = 6 V

−430

−600

A

IL

Low-level input current

SENSEn

VSENSE1,2,3 = 0 V

−1

1

µA

IDD

Supply current

40

µΑ

Ci

Input capacitance

VI = 0 V to VDD

10

pF

NOTES:

2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V

3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1

µF) should be placed close to the supply terminals.