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A1242EUA-I1-T Datasheet(PDF) 9 Page - Allegro MicroSystems

Part # A1242EUA-I1-T
Description  Two-Wire Chopper-Stabilized Hall Effect Latch
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A1242EUA-I1-T Datasheet(HTML) 9 Page - Allegro MicroSystems

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A1242-DS
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
Allegro MicroSystems, Inc.
Two-Wire Chopper-Stabilized Hall Effect Latch
A1242
Power Derating
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RθJC, is
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN
× IIN
(1)
ΔT = PD
× RθJA
(2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 6 mA, and RθJA = 165 °C/W, then:
PD = VCC
× ICC = 12 V × 6 mA = 72 mW
ΔT = PD
× RθJA = 72 mW × 165 °C/W = 12°C
TJ = TA + ΔT = 25°C + 12°C = 37°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RθJA and TA.
Example: Reliability for VCC at TA=150°C, package LH, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA=228°C/W, TJ(max) =165°C, VCC(max)= 24 V, and
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax÷RθJA =15°C÷228 °C/W=66mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max)= 66mW÷17mA=3.9 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.


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