8

Applications Information

Power Supplies and Circuit Layout

The EL5181 comparator operates with single and dual sup-

the comparator is supplied by a single supply from 2.7V to

5V. The rail to rail output swing enables direct connection of

the comparator to both CMOS and TTL logic circuits. As with

many high speed devices, the supplies must be well

bypassed. Elantec recommends a 4.7µF tantalum in parallel

with a 0.1µF ceramic. These should be placed as close as

possible to the supply pins. Keep all leads short to reduce

stray capacitance and lead inductance. This will also mini-

mize unwanted parasitic feedback around the comparator.

The device should be soldered directly to the PC board

instead of using a socket. Use a PC board with a good,

unbroken low inductance ground plane. Good ground plane

construction techniques enhance stability of the

comparators.

Input Voltage Considerations

output still responds correctly to a small differential input sig-

nal. The differential input stage is a pair of PNP transistors,

therefore, the input bias current flows out of the device.

When either input signal falls below the negative input volt-

age limit, the parasitic PN junction formed by the substrate

and the base of the PNP will turn on, resulting in a significant

increase of input bias current. If one of the inputs goes above

the positive input voltage limit, the output will still maintain

the correct logic level as long as the other input stays within

the input range. However, the propagation delay will

increase. When both inputs are outside the input voltage

range, the output becomes unpredictable. Large differential

voltages greater than the supply voltage should be avoided

to prevent damages to the input stage.

Input Slew Rate

Most high speed comparators oscillate when the voltage of

one of the inputs is close to or equal to the voltage on the

other input due to noise or undesirable feedback. For clean

output waveform, the input must meet certain minimum slew

rate requirements. In some applications, it may be helpful to

apply some positive feedback (hysteresis) between the out-

put and the positive input. The hysteresis effectively causes

one comparator's input voltage to move quickly past the

other, thus taking the input out of the region where oscillation

occurs. For the EL5181, the propagation delay increases

when the input slew rate increases for low overdrive volt-

ages. With high overdrive voltages, the propagation delay

does not change much with the input slew rate.

Latch Pin Dynamics

The EL5181 contains a “transparent” latch for each channel.

The latch pin is designed to be driven with either a TTL or

CMOS output. When the latch is connected to a logic high

level or left floating, the comparator is transparent and imme-

diately responds to the changes at the input terminals. When

the latch is switched to a logic low level, the comparator out-

put remains latched to its value just before the latch’s high-

to-low transition. To guarantee data retention, the input sig-

nal must remain the same state at least 1ns (hold time) after

the latch goes low and at least 2ns (setup time) before the

latch goes low. When the latch goes high, the new data will

appear at the output in approximately 6ns (latch propagation

delay).

Hysteresis

Hysteresis can be added externally. The following two meth-

ods can be used to add hysteresis.

Inverting comparator with hysteresis:

greater than the input bias current of the comparator:

where:

Non inverting comparator with hysteresis:

bias current in order to minimize errors. The calculation of

the resistor values as follows:

order to minimize the propagation delay time.

+

-

V

TH

V

REF

R

1

R

1

R

2

+

---------------------

×

=

R

3

V

O

V

H

--------

R

1

(

R

||

×

=

R

(

()-V

V

TH

R

1

-----------







÷





 V

R

3

-----------------------------------







+

=

+

-

R

3

V

(

R

1

V

H

--------

×

=

EL5181