3

Closed-Loop AC Electrical Specifications

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

Oscillator Initial Accuracy

105

117

130

kHz

Minimum Oscillator Sync Width

25

ns

Soft Start Slope

0.5

V/ms

FET Break Before Make Delay

15

ns

High Side FET Minimum On Time

150

ns

Maximum Duty Cycle

95

%

Pin Descriptions

PIN

NUMBER

PIN NAME

PIN FUNCTION

1

SGND

Control circuit negative supply.

2

COSC

Oscillator timing capacitor. FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in µF.

3

VDD

Control circuit positive supply.

4

PGND

Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.

5

PGND

Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.

6

VIN

Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.

7

VIN

Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.

8

EN

Chip Enable, active high. A 2µA internal pull-up current enables the device if the pin is left open.

9

PGND

Ground return of the regulator.

10

VHI

Positive supply of the high-side driver.

11

LX

Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.

12

LX

Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.

13

VDRV

Positive supply of the low-side driver and input voltage for the high-side boot strap.

14

FB

Voltage feedback input. Connected to an external resistor divider between VOUT and GND. A 125nA pull-up current

forces VOUT to VS in the event that FB is floating.

15

VREF

Bandgap reference bypass capacitor. Typically 0.1µF to GND.

16

PGND

Ground return of the regulator.

EL7551