6

FN7431.5

August 16, 2005

Applications Information

Product Description

The EL7534 is a synchronous, integrated FET 600mA step-

down regulator which operates from an input of 2.5V to 6V.

The output voltage is user-adjustable with a pair of external

resistors.

The internally-compensated controller makes it possible to

use only two ceramic capacitors and one inductor to form a

complete, very small footprint 600mA DC:DC converter.

Start-Up and Shut-Down

approximately 2.4V, the regulator begins to switch. The

output voltage is gradually increased to ensure proper soft-

start operation.

When the EN pin is connected to a logic low, the EL7534 is

in the shut-down mode. All the control circuitry and both

total input current is less than 1µA.

When the EN reaches logic HI, the regulator repeats the

start-up procedure, including the soft-start function.

PWM Operation

In the PWM mode, the P channel MOSFET and N channel

MOSFET always operate complementary. When the

PMOSFET is on and the NMOSFET off, the inductor current

increases linearly. The input energy is transferred to the

output and also stored in the inductor. When the P channel

MOSFET is off and the N channel MOSFET on, the inductor

current decreases linearly, and energy is transferred from

the inductor to the output. Hence, the average current

through the inductor is the output current. Since the inductor

and the output capacitor act as a low pass filter, the duty

The output LC filter has a second order effect. To maintain

the stability of the converter, the overall controller must be

compensated. This is done with the fixed internally

compensated error amplifier and the PWM compensator.

Because the compensations are fixed, the values of input

and output capacitors are 10µF to 22µF ceramic. The

inductor is nominally 1.8µH, though 1.5µA to 2.2µH can be

used.

100% Duty Ratio Operation

EL7534 utilizes CMOS power FET's as the internal

synchronous power switches. The upper switch is a PMOS

and lower switch a NMOS. This not only saves a boot

capacitor, it also allows 100% turn-on of the upper PFET

the PFET on-resistance, nominal 70m

Ω at room temperature

with tempco of 0.2m

Ω/°C.

As the input voltage drops gradually close or even bellow the

condition, the upper PFET needs some minimum turn-off

time if it is turned off. This off-time is related to input/output

conditions. This makes the duty ratio appears randomly and

increases the output ripple somewhat until the 100% duty

ratio is reached. Larger output capacitor could reduce the

random-looking ripple. Users need to verify if this condition

FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

otherwise noted.

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.7

0.6

0.4

0.3

0.2

0.1

0

0

255075

100

150

AMBIENT TEMPERATURE (°C)

85

607mW

θ

206

°C

/W

MS

OP

10

0.5

125

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

1

0.4

0

0

255075

100

150

AMBIENT TEMPERATURE (°C)

85

1.087W

θ

115

°C

/W

MS

OP

10

0.8

0.2

0.6

125

+

() I

O

×

–

=

EL7534