Electronic Components Datasheet Search |
|
FAN5182 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
|
FAN5182 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 18 page 10 www.fairchildsemi.com FAN5182 Rev. 1.0.1 Voltage Control Loop A high gain-bandwidth voltage error amplifier is used for the voltage control loop. The non-inverting input of the error ampli- fier is derived from the internal 800mV reference. The output of the error amplifier, the COMP pin sets the termination voltage for the internal PWM ramps plus sensed phase current. The inverting input (FB) is tied to the center point of a resistor divider from the output voltage sense point. The closed loop compensation is realized through the compensator networks connecting to the FB and COMP pins. Soft Start The soft-start rise time of the output voltage is set by a parallel capacitor and resistor between the DELAY pin and ground. The resistor capacitor (RC) time constant also determines the cur- rent limit latch off delay time as explained in the following sec- tion. In UVLO or when EN is logic low, the DELAY pin is held to ground. After the UVLO threshold is reached and EN is in logic high state, the DELAY capacitor is charged with an internal 20µA current source. The output voltage follows the ramping voltage on the DELAY pin to limit the inrush current. The soft- start time depends on the value of CDLY, with a secondary effect from RDLY. If either EN is logic low or VCC drops below UVLO, the DELAY capacitor resets to ground, and is ready for another soft-start cycle. Figure 6. Typical Startup Waveforms shows a typical soft-start sequence for the FAN5182. Figure 6. Typical Startup Waveforms Current Limit and Latch-off Protection The FAN5182 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4mV/µA. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the COMP voltage to maintain the power supply output current at the over current level. After the limit is reached, the 3V pull-up voltage source on the DELAY pin is disconnected, and the external DELAY capacitor discharges through the external resistor. A comparator monitors the DELAY pin voltage and shuts off the controller when the voltage drops below 1.8V. The current limit latch-off delay time is therefore set by the RC time constant discharging the DELAY voltage from 3V to 1.8V. Typical over-current latch-off wave- forms are shown in Figure 7. Figure 7. Over-current Latch-off Waveforms The controller continues to switch all phases during the latch-off delay time. If the over-current condition is removed before the 1.8V DELAY threshold being reached, the controller will resume its normal operation. The over current recovery characteristic also depends on the state of PWRGD. If the output voltage is within the PWRGD window during over current, the controller resumes normal operation once over current condition being removed. However, if over current causes the output voltage to drop below the PWRGD threshold, a soft-start cycle will be initi- ated. The latch-off function can be reset by either removing and reap- plying VCC to the FAN5182 or by pulling the EN pin low for short time. To disable the over current latch-off function, the external resistor connecting between the DELAY pin and ground should be removed, and a high value resistor (>1M Ω) should be con- nected from the DELAY pin to VCC. This prevents the DELAY capacitor from discharging, so the 1.8V threshold can never be reached. This pull-up resistor has some impact to the soft-start time, because the current through this pull-up resistor adds additional current to the internal 20µA soft-start current. During start-up when the output voltage is below 200mV, a sec- ondary current limit is activated. This is necessary because the voltage swing of CSCOMP cannot go below ground. This sec- ondary current limit clamps the COMP voltage to 2V. An inherent per phase current limit protects individual phase if one or more phases cease to function because of a faulty com- ponent. This limit is based on the maximum normal mode COMP voltage. |
Similar Part No. - FAN5182 |
|
Similar Description - FAN5182 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |