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ST7DALI Datasheet(PDF) 52 Page - STMicroelectronics |
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ST7DALI Datasheet(HTML) 52 Page - STMicroelectronics |
52 / 141 page ST7DALI 52/141 WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 12 .Watchdog Timing): – The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme- diate reset – The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software re- set (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. Table 12.Watchdog Timing Notes: 1. The timing variation shown in Table 12 is due to the unknown status of the prescaler when writing to the CR register. 2. The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the Option Byte description in section 15 on page 130. 11.1.4.1 Using Halt Mode with the WDG (WDGHALT option) If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruc- tion to refresh the WDG counter, to avoid an unex- pected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode. fCPU = 8MHz WDG Counter Code min [ms] max [ms] C0h 1 2 FFh 127 128 1 |
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