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HD6412350 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6412350 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 989 page iii Section 5 Interrupt Controller......................................................................................... 91 5.1 Overview............................................................................................................................ 91 5.1.1 Features ................................................................................................................. 91 5.1.2 Block Diagram...................................................................................................... 92 5.1.3 Pin Configuration.................................................................................................. 93 5.1.4 Register Configuration.......................................................................................... 93 5.2 Register Descriptions ......................................................................................................... 94 5.2.1 System Control Register (SYSCR)....................................................................... 94 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 95 5.2.3 IRQ Enable Register (IER) ................................................................................... 96 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97 5.2.5 IRQ Status Register (ISR) .................................................................................... 98 5.3 Interrupt Sources................................................................................................................ 99 5.3.1 External Interrupts ................................................................................................ 99 5.3.2 Internal Interrupts.................................................................................................. 100 5.3.3 Interrupt Exception Handling Vector Table ......................................................... 100 5.4 Interrupt Operation............................................................................................................. 104 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 104 5.4.2 Interrupt Control Mode 0...................................................................................... 107 5.4.3 Interrupt Control Mode 2...................................................................................... 109 5.4.4 Interrupt Exception Handling Sequence ............................................................... 111 5.4.5 Interrupt Response Times ..................................................................................... 113 5.5 Usage Notes ....................................................................................................................... 114 5.5.1 Contention between Interrupt Generation and Disabling ..................................... 114 5.5.2 Instructions that Disable Interrupts....................................................................... 115 5.5.3 Times when Interrupts are Disabled ..................................................................... 115 5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 115 5.6 DTC and DMAC Activation by Interrupt.......................................................................... 116 5.6.1 Overview............................................................................................................... 116 5.6.2 Block Diagram...................................................................................................... 116 5.6.3 Operation .............................................................................................................. 117 Section 6 Bus Controller.................................................................................................. 119 6.1 Overview............................................................................................................................ 119 6.1.1 Features ................................................................................................................. 119 6.1.2 Block Diagram...................................................................................................... 121 6.1.3 Pin Configuration.................................................................................................. 122 6.1.4 Register Configuration.......................................................................................... 123 6.2 Register Descriptions ......................................................................................................... 124 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 124 6.2.2 Access State Control Register (ASTCR) .............................................................. 125 6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 126 6.2.4 Bus Control Register H (BCRH) .......................................................................... 130 |
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