SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995

Copyright

1

POST OFFICE BOX 655303

Conversions

Outputs on Last Stage

Small-Outline (D) Packages and Standard

Plastic (N) 300-mil DIPs

description

outputs, J-K serial (J, K) inputs, shift/load control (SH/LD) input, and a direct overriding clear (CLR). The

registers have two modes of operation:

Parallel loading is accomplished by applying the four bits of data and taking SH/LD low. The data is loaded into

the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During

loading, serial data flow is inhibited.

Shifting is accomplished synchronously when SH/LD is high. Serial data for this mode is entered at the J-K

inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function

table.

The SN74AS195 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

SH/LD

CLK

SERIAL

PARALLEL

Q

Q

Q

Q

Q

CLR

SH/LD

CLK

J

K

A

B

C

D

QA

QB

QC

QD

QD

L

X

X

X

X

X

X

X

X

L

L

L

L

H

H

L

↑

X

Xa

bc

d

a

bc

d

d

H

HL

X

XX

XX

X

QA0

QB0

QC0

QD0

QD0

H

H

↑

L

HX

XX

X

QA0

QA0

QBn

QCn

QCn

H

H

↑

L

LX

XX

X

L

QAn

QBn

QCn

QCn

H

H

↑

H

HX

XX

X

H

QAn

QBn

QCn

QCn

H

H

↑

H

L

X

X

X

X

QAN

QAn

QBn

QCn

QCn

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

J

K

A

B

C

D

GND

CLK

SH/LD

D OR N PACKAGE

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