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IDT72V70210BC Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V70210BC Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 19 page 11 COMMERCIALTEMPERATURERANGE IDT72V70210 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 ST-BUS F0i RX Stream 5714 drw 05 Bit 7 Bit 7 CLK Bit 7 Bit 7 denotes the 3/4 point of the bit cell offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 GCI F0i Bit 0 Bit 0 CLK Bit 0 Bit 0 denotes the 3/4 point of the bit cell offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 RX Stream RX Stream RX Stream RX Stream RX Stream RX Stream RX Stream MeasurementResultfrom Corresponding InputStream Frame Delay Bits Offset Bits Offset FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn No clock period shift (Default) 10000000 + 0.5 clock period shift 00000001 + 1.0 clock period shift 10010010 + 1.5 clock period shift 00010011 + 2.0 clock period shift 10100100 + 2.5 clock period shift 00100101 + 3.0 clock period shift 10110110 + 3.5 clock period shift 00110111 + 4.0 clock period shift 11001000 + 4.5 clock period shift 01001001 TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS (FD11, FD2-0) Figure 2. Examples for Input Offset Delay Timing |
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