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TSC51C1XXX-16CHR Datasheet(PDF) 10 Page - TEMIC Semiconductors |
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TSC51C1XXX-16CHR Datasheet(HTML) 10 Page - TEMIC Semiconductors |
10 / 31 page TSC8051C1 Rev. D (14 Jan. 97) 10 MATRA MHS 6.7. Memory organization The memory organisation of the TSC8051C1 is the same as in the 80C51, with the exception that the TSC8051C1 has 8k bytes ROM, 256 bytes RAM, and additional SFRs. Details of the differences are given in the following paragraphs. In the TSC8051C1, the lowest 8k of the 64k program memory address space is filled by internal ROM. Depending on the package used, external access is available or not. By tying the EA pin high, the processor fetches instructions from internal program ROM. Bus expansion for accessing program memory from 8k upward is automatic since external instruction fetches occur automatically when the program counter exceeds 1FFFh. If the EA pin is tied low, all program memory fetches are from external memory. The execution speed is the same regardless of whether fetches are from external or internal program memory. If all storage is on–chip, then byte location 1FFFh should be left vacant to prevent an undesired pre–fetch from external program memory address 2000h. Certain locations in program memory are reserved for specific purposes. Locations 0000h to 0002h are reserved for the initialisation program. Following reset, the CPU always begins execution at location 0000h. Locations 0003h to 0032h are reserved for the six interrupt request service routines. The internal data memory space is divided into a 256–bytes internal RAM address space and a 128 bytes special function register address space. The internal data RAM address space is 0 to FFh. Four 8–bit register banks occupy locations 0 to 1Fh. 128 bit locations of the internal data RAM are accessible through direct addressing. These bits reside in 16 bytes of internal RAM at location 20h to 2Fh. The stack can be located anywhere in the internal data RAM address space by loading the 8–bit stack pointer (SP SFR). The SFR address space is 100h to 1FFh. All registers except the program counter and the four 8–bit register banks reside in this address space. Memory mapping of the SFRs allows them to be accessed as easily as internal RAM, and as such, they can be operated on by most instructions.The mapping in the SFR address space of the 43 SFRs is shown in Table 2. The SFR names in italic are TSC8051C1 new SFRs and are described in Peripherals Functional Description section. The SFR names in bold are bit addressable. |
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