RTR-10
RTA(4:0) = 04 (hex) = 00100
RTPTY = 1 (hex) = 1
Sum of 1’s = 2 (even), Status Register bit 12 = 1
The RTR checks the Terminal Address and parity on Master
Reset. With Broadcast disabled, RTA (4:0) = 11111 operates
as a normal RT address.
1.7 Internal Self-Test
Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The self-test
capability of the RTR is based on the fact that the MIL-STD-
1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTR will recognize the
incoming status word as a command word and thus cause
the RTR to transmit another status word. After the host
invokes self-test, the RTR self-test logic forces a status word
transmission even though the RTR has not received a valid
command. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
self-test is controlled by the host periodically changing the
bit patterns in the status word being transmitted. Writing to
the Control Register bits 2, 3, 4, 7, and 8 changes the status
word. Monitor the self-test by sampling either the Status
Register or the external status pins (i.e., Command Strobe
(COMSTR), Transmit/Receive (T/R)). For more detailed
explanation of internal self-test, consult UTMC publication
RTR/RTS Internal Self-Test Routine.
1.8 Power-up and Master Reset
After power-up, reset initializes the part with its biphase
ports enabled, latches the Terminal Address, and turns on
the busy option. The device is ready to accept commands
from the MIL-STD-1553B bus. The busy flag is asserted
while the host is loading the message pointers and messages.
After this task is completed, the host removes the busy
condition via a Control Register write to the RTR. On
power-up if the terminal address parity (odd) is incorrect,
the biphase inputs are disabled and the message error pin
(MERR) is asserted. This condition can also be monitored
via bit 12 of the Status Register. The MERR pin is negated
on reception of first valid command.
1.9 Encoder and Decoder
The RTR interfaces directly to a bus transmitter/ receiver
via the RTR Manchester II encoder/decoder. The UT1553B
RTR receives the command word from the MIL-STD-
1553B bus and processes it either by the primary or
secondary decoder. Each decoder checks for the proper sync
pulse and Manchester waveform, edge skew, correct number
of bits, and parity. If the command is a receive command,
the RTR processes each incoming data word for correct
format and checks the control logic for correct word count
and contiguous data. If an invalid message error is detected,
the message error pin is asserted, the RTR ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.
The RTR automatically compares the transmitted word
(encoder word) to the reflected decoder word by way of the
continuous loop-back feature. If the encoder word and
reflected word do not match, the transmitter error pin
(TXERR) is asserted. In addition to the loop-back compare
test, a timer precludes a transmission greater than 760
µs by
the assertion of Fail-safe Timer (TIMERON). This timer is
reset upon receipt of another command.
1.10 RT-RT Transfer Compare
The RT-to-RT Terminal Address compare logic makes sure
that the incoming status word’s Terminal Address matches
the Terminal Address of the transmitting RT specified in the
command word. An incorrect match results in setting the
Message Error bit and suppressing transmission of the status
word. (RT-to-RT transfer time-out = 54
µs)
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