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WS128K32V-XXX
WS32K32-XHX
FIG. 4
TIMING WAVEFORM - READ CYCLE
FIG. 6
WRITE CYCLE - CS CONTROLLED
FIG. 5
WRITE CYCLE - WE CONTROLLED
ADDRESS
DATA I/O
WRITE CYCLE 1, WE CONTROLLED
tAW
tCW
tAH
tWP
tDW
tWHZ
tAS
tOW
tDH
tWC
DATA VALID
CS
WE
ADDRESS
DATA I/O
WRITE CYCLE 2, CS CONTROLLED
tAW
tAS
tCW
tAH
tWP
tDH
tDW
tWC
CS
WE
DATA VALID
ADDRESS
DATA I/O
READ CYCLE 2 (WE = VIH)
tAA
tACS
tOE
tCLZ
tOLZ
tOHZ
tRC
DATA VALID
HIGH IMPEDANCE
CS
OE
tCHZ
ADDRESS
DATA I/O
READ CYCLE 1 (CS = OE = VIL, WE = VIH)
tAA
tOH
tRC
DATA VALID
PREVIOUS DATA VALID