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MSP430F5507 Datasheet(PDF) 55 Page - Texas Instruments |
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MSP430F5507 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 125 page  55 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated 6.8 RAM (Link to User's Guide) The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data are lost. Features of the RAM include: • RAM has n sectors. The size of a sector can be found in Section 6.4. • Each sector 0 to n can be completely disabled; however, data retention is lost. • Each sector 0 to n automatically enters low-power retention mode when possible. • For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required. 6.9 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide. 6.9.1 Digital I/O (Link to User's Guide) Up to six 8-bit I/O ports are implemented: for 64-pin options, P1, P2, P4, P6, and are complete, P5 is reduced to 6-bit I/O, and P3 to 5-bit I/O. For 48-pin options, P6 is reduced to 4-bit I/O, P2 to 1-bit I/O, and P3 is completely removed. Port PJ contains four individual I/O ports, common to all devices. • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Pullup or pulldown on all ports is programmable. • Drive strength on all ports is programmable. • Edge-selectable interrupt and LPM4.5 wake-up input capability is available for all bits of ports P1 and P2. • Read and write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC). 6.9.2 Port Mapping Controller (Link to User's Guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see Table 6-7). Table 6-8 lists the default settings for all pins that support port mapping. Table 6-7. Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS 1 PM_CBOUT0 – Comparator_B output PM_TB0CLK TB0 clock input – 2 PM_ADC10CLK – ADC10CLK PM_DMAE0 DMAE0 input – 3 PM_SVMOUT – SVM output PM_TB0OUTH TB0 high impedance input TB0OUTH – 4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0 5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1 6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2 7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3 8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4 9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5 10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6 |
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