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MSP430FG479 Datasheet(PDF) 51 Page - Texas Instruments |
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MSP430FG479 Datasheet(HTML) 51 Page - Texas Instruments |
51 / 97 page 51 MSP430FG479, MSP430FG478, MSP430FG477 www.ti.com SLAS580E – OCTOBER 2008 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430FG479 MSP430FG478 MSP430FG477 Detailed Description Copyright © 2008–2020, Texas Instruments Incorporated (1) Access and key violations, KEYV and ACCVIFG. (2) Multiple source flags (3) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (4) Interrupt flags are located in the module. (5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. (6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. 6.4 Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up. Table 6-3. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-Up External Reset Watchdog Flash Memory PC Out-of-Range(1) PORIFG RSTIFG WDTIFG KEYV (2) Reset 0FFFEh 15, highest NMI Oscillator Fault Flash Memory Access Violation NMIIFG (2) (3) OFIFG(2) (3) ACCVIFG(2) (4) (Non)maskable (Non)maskable (Non)maskable 0FFFCh 14 Timer_B3 TBCCR0 CCIFG0(4) Maskable 0FFFAh 13 Timer_B3 TBCCR1 CCIFG1 and TBCCR2 CCIFG2, TBIFG(2)(4) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog Timer+ WDTIFG Maskable 0FFF4h 10 USCI_A0, USCI_B0 Receive, USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG(2)(5) Maskable 0FFF2h 9 USCI_A0, USCI_B0 Transmit, USCI_B0 I2C receive/transmit UCA0TXIFG, UCB0TXIFG (2)(6) Maskable 0FFF0h 8 SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG (2) (4) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG0(4) Maskable 0FFECh 6 Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG(2) (4) Maskable 0FFEAh 5 I/O Port P1 (8 Flags) P1IFG.0 to P1IFG.7(2) (4) Maskable 0FFE8h 4 DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0FFE6h 3 Maskable 0FFE4h 2 I/O Port P2 (8 Flags) P2IFG.0 to P2IFG.7 (2) (4) Maskable 0FFE2h 1 Basic Timer 1, RTC BTIFG Maskable 0FFE0h 0, lowest |
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