PG 2

Output

PG 1

11

SN74HCS03-Q1

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SCLS759 – APRIL 2020

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Typical Application (continued)

9.2.1.2 Input Considerations

not exceed the maximum input voltage range found in the Absolute Maximum Ratings.

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

SN74HCS03-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ

resistor value is often used due to these factors.

The SN74HCS03-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.

Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude

Characteristics. This hysteresis value will provide the peak-to-peak limit.

Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without

causing huge increases in power consumption. The typical additional current caused by holding an input at a

Refer to the Feature Description for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the

relationship between output voltage and current for this device.

Open-drain outputs can be directly connected together to produce a wired-AND. This is possible because the

outputs cannot source current, and thus can never be in bus-contention.

Unused outputs can be left floating.

Refer to Feature Description for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

2. Ensure the capacitive load at the output is

≤ 70 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS03-

Q1 to the receiving device.

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation

9.2.3 Application Curves

Figure 10. Application timing diagram