W83769

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1.2 Chip Decode and Select Logic

The W83769 contains all required chip select and decode logic needed to function without any

additional buffering or interface logic to the local bus. This includes all address decoding, data

buffering, and control logic.

1.3 Direct Drive IDE Disk Interface

The W83769 provides a slew-rate-controlled direct drive interface to four IDE drives. The interface

conforms to relevant industry standards, including the ANSI ATA Rev. 3.0 standard. Up to four

W83769 devices, and therefore 16 IDE drives, can be interfaced to the local bus. Additional drives

can reside on expansion buses. Drive selection and switching are handled by software.

Each device permits either of the two interfaced IDE ports to be assigned and addressed as the

primary or secondary port. Each port can support two drives, which can be assigned as the master

drive (drive 0) or slave drive (drive 1). Individual IDE disk drive performance can be optimized

through the W83769's programmable registers. Each drive's command active and recovery timing,

address setup and hold, and data read/write active and recovery timing may be controlled

independently.

1.4 Four-level Read Ahead Buffer and Counter

The W83769's read-ahead feature significantly enhances disk drive read performance. In pipelined

read-ahead mode, when the host CPU is occupied with other or previous data transfers, the IDE

controller can automatically request and concurrently transfer additional data from the disk drive.

These data are stored in the device's four-level FIFO read-ahead buffer.The controller will continue to

read data from the drive as long as the buffer is not full, the read-ahead counter is not zero, and the

host CPU continues to request data. Data transfer sizes are determined by the host CPU request and

can be word or double-word.

A programmable read-ahead counter is used in conjunction with the read-ahead buffer to regulate the

flow of data from the disk drive. The counter is normally initialized with the number of bytes per

sector. This is determined from the disk formatting and can be different for each drive. As data is

transferred, the counter is decremented to zero. It is then reinitialized for the next sector transfer.

1.5 Four-level Posted Write Buffer

The W83769 also contains a four-level FIFO posted-write buffer which can be used by the CPU to

pipeline data to the disk drive, thereby significantly increasing throughput. The CPU data are written

to the posted-write buffer. Concurrently, data are written to the disk drive by the IDE controller at the

appropriate data transfer rate. While the buffered data are waiting to be written, the CPU is left free to

fetch additional data for the next transfer.

1.6 Interrupt Operation

To ensure proper interrupt operation between the IDE drives and the host CPU, the drives' interrupts

can be passed through the W83769. The interrupts are input on the DIRQ pin and asynchronously

output to the host chipset on the HIRQ pin as IRQ14, the standard IDE PC/AT interrupt. If four drives,

i.e., two drive cables, are present, the interrupts from both pairs of drives can be connected to HIRQ.

The interrupt status of individual drives can be read from the general purpose configuration register,

RX50, bit 2. A 10K ohm pullup should be connected to the HIRQ input to prevent floating.

Alternatively, with four drives present, the interrupt from each pair of drives can be connected directly

to the host CPU chipset IRQ14 and IRQ15.