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TMS320VC5402A Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320VC5402A Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 98 page  www.ti.com TMS320VC5402A Fixed-Point Digital Signal Processor SPRS015E – SEPTEMBER 2001 – REVISED JANUARY 2005 5-13 I/O Write With Externally Generated Wait States ............................................................................. 72 5-14 HOLD and HOLDA Timings (HM = 1) .......................................................................................... 73 5-15 Reset and BIO Timings ........................................................................................................... 74 5-16 Interrupt Timing .................................................................................................................... 75 5-17 MP/MC Timing ..................................................................................................................... 75 5-18 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings ................................................. 76 5-19 External Flag (XF) Timing ........................................................................................................ 77 5-20 TOUT Timing ...................................................................................................................... 77 5-21 McBSP Receive Timings ......................................................................................................... 79 5-22 McBSP Transmit Timings ........................................................................................................ 80 5-23 McBSP General-Purpose I/O Timings .......................................................................................... 81 5-24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ..................................................... 82 5-25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ..................................................... 83 5-26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ..................................................... 84 5-27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ..................................................... 85 5-28 HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low) ................................................ 88 5-29 HPI-8 Mode Timing, Using HCS to Control Accesses ....................................................................... 89 5-30 HPI-8 Mode, HINT Timing ....................................................................................................... 89 5-31 GPIOx Timings .................................................................................................................... 89 5-32 HPI-16 Mode, Nonmultiplexed Read Timings ................................................................................. 91 5-33 HPI-16 Mode, Nonmultiplexed Write Timings ................................................................................. 92 5-34 HPI-16 Mode, HRDY Relative to CLKOUT .................................................................................... 92 6 List of Figures |
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